An efficient VLSI architecture for block matching motion estimation

被引：0
|
作者：
Lee, HY [1 ]
Kim, JW [1 ]
Ohk, YM [1 ]
Lee, KW [1 ]
机构：
[1] ELECT & TELECOMMUN RES INST,TAEJON 305600,SOUTH KOREA
来源：
DIGITAL COMPRESSION TECHNOLOGIES AND SYSTEMS FOR VIDEO COMMUNICATIONS | 1996年 / 2952卷
关键词：
block matching motion estimation; linear systolic array; pipeline operations; VLSI architecture;
D O I：
10.1117/12.251322
中图分类号：
O43 [光学];
学科分类号：
070207 ; 0803 ;
摘要：
引用
收藏
页码：575 / 581
页数：7
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