共 50 条
- [43] Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS, 2009, : 164 - 171
- [44] Verification of RTL generated from scheduled behavior in a high-level synthesis flow 1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, : 517 - 524
- [45] A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis 11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, : 494 - 499
- [46] Abstract State Machines as an Intermediate Representation for High-level Synthesis 2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 1406 - 1411
- [47] Coordinated transformations for high-level synthesis of high performance microprocessor blocks 39TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2002, 2002, : 898 - 903
- [48] High-level synthesis using predefined IP-s Periodica Polytechnica Electrical Engineering, 2004, 46 (3-4): : 123 - 136
- [50] The amplicon-plus system for high-level expression of transgenes in plants Nature Biotechnology, 2002, 20 : 622 - 625