Partially detectable faults in synchronous sequential circuits

被引：0
|
作者：
Dawoud, DS
机构：
来源：
AFRICON '96 - 1996 IEEE AFRICON : 4TH AFRICON CONFERENCE IN AFRICA, VOLS I & II: ELECTRICAL ENERGY TECHNOLOGY; COMMUNICATION SYSTEMS; HUMAN RESOURCES | 1996年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Faults in sequential circuits are studied. Undetectable and redundant faults under different modes of operation are analysed. Undetectable faults are split into two classes: operationally redundant faults and partially redundant faults. Operationally redundant faults are defined as faults that are never manifested as faulty output during normal operation. Partially redundant faults are defined as faults that can affect the output sequence under certain initial conditions otherwise it is undetectable. Faults in sequential circuits are, accordingly, classified into three classes: detectable, partially detectable and operationally redundant. Test generation strategies and the relation between test sequences under different modes of operation are analysed.
引用
收藏
页码：795 / 800
页数：6
相关论文
共 50 条
  • [1] On removing redundant faults in synchronous sequential circuits
    Lin, XJ
    Pomeranz, I
    Reddy, SM
    [J]. 16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1998, : 168 - 175
  • [2] On the detection of reset faults in synchronous sequential circuits
    Pomeranz, I
    Reddy, SM
    [J]. TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 470 - 474
  • [3] CLASSIFICATION OF FAULTS IN SYNCHRONOUS SEQUENTIAL-CIRCUITS
    POMERANZ, I
    REDDY, SM
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1993, 42 (09) : 1066 - 1077
  • [4] On finding undetectable and redundant faults in synchronous sequential circuits
    Lin, XJ
    Pomeranz, I
    Reddy, SM
    [J]. INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 498 - 503
  • [5] On redundant path delay faults in synchronous sequential circuits
    Tekumalla, RC
    Menon, PR
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2000, 49 (03) : 277 - 282
  • [6] MODELING AND TESTING FOR TIMING FAULTS IN SYNCHRONOUS SEQUENTIAL-CIRCUITS
    MALAIYA, YK
    NARAYANASWAMY, R
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 1984, 1 (04): : 62 - 74
  • [7] Fault simulation method for crosstalk faults in synchronous sequential circuits
    Itazaki, N
    Idomoto, Y
    Kinoshita, K
    [J]. PROCEEDINGS OF THE TWENTY-SIXTH INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, 1996, : 38 - 43
  • [8] An approach to diagnose logical faults in partially observable sequential circuits
    Yamazaki, K
    Yamada, T
    [J]. SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 168 - 173
  • [9] A fault simulation method for crosstalk faults in synchronous sequential circuits
    Itazaki, N
    Idomoto, Y
    Kinoshita, K
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1997, E80D (01) : 38 - 43
  • [10] Analysis and testing of bridging faults in CMOS synchronous sequential circuits
    Miura, Y
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2004, E87D (03): : 564 - 570
12345