Chip/Package Interactions on advanced Flip-Chip packages: Mechanical Investigations on Copper pillar bumping

New customer demands for improved performance of ICs constantly require development of novel assembly processes. Hence, following the introduction of copper pillar bump, some Chip-package compatibility concerns are observed while processing, such as reflow or thermal cycles. In this paper, the mechanical behavior of the copper pillar is particularly studied. The effectiveness of a repassivation layer, namely polyimide (PI), to lower the stress within pad structure is assessed experimentally thanks to dedicated test vehicles. Results show that the polyimide introduction is not always relevant since it induceds the lowest yield. The typical observed failure modes are described. In order to get a better understanding of the involved mechanisms, Finite Element simulations are performed. Numerical results show that the Copper/Aluminum interface is one of the main criteria to assess the stress field within the pad. By introducing the polyimide layer, the copper pillar section is reduced and then, leads to higher stress concentration within the pad structure. Then, the effect of the polyimide is compared for two bump configurations: solder and copper pillar. It is shown that in case of solder bump, the repassivation layer is much more stressed and allows to limit the stress within the interconnect stack compared to the unpassivated configuration. Distinct behavior is then observed between solder and copper pillar bumps concerning the PI implementation. At last, the effect of fine pitch bumping is investigated and any interactions are found for the considered values. Thanks to these investigations, differences between solder bump and copper pillar bumps are shown and the needs of dedicated developments for copper pillar bump integration are thus underlined.