Reliability of Cu Pillar Bumps for Flip-Chip Packages with Ultra Low-k Dielectrics

The reliability of Cu/low k interconnect structures using Cu pillar bumps was investigated in this paper. First the characteristics related to electromigration (EM) of Cu pillars with Sn-Ag tips were studied and compared with full Pb-free Sn-Ag solder bumps. The simulation results revealed a significant reduction in the current crowding when Sn-Ag C4 solder was replaced by Cu pillar structures. As a result, the current-induced Joule heating and local temperature gradients were reduced in the Cu pillar structure. This was followed by a study of the impact of the Cu pillar bumps on the mechanical reliability of ultra low-k dielectrics. The crack driving force induced by chip-package-interaction (CPI) for delamination in the ultra low-k interconnect structure was evaluated using a 3D sub-modeling technique. The energy release rate was found to increase significantly for packages with Cu pillar bumps compared with those with Pb-free solder only. Finally, the characteristics of thermal fatigue life of Cu pillar bumps were investigated based on Darveaux's strain energy density model. The results showed that the fatigue life of the solder tips adjacent to Cu pillar could be improved by reducing the Cu pillar height in relation to the solder tip height. Structural optimization of Cu pillar bumps to improve the mechanical stability of packages with ultra low-k dielectrics in the chips was discussed.