Bonding Based Channel Transfer and Low Temperature Process for Monolithic 3D Integration Platform Development

被引：0
|
作者：
Choi, Rino [1 ]
Yu, Hyun-Yong [2 ]
Kim, Hyungsub [3 ]
Ryu, Han-Youl [4 ]
Bae, Hee-Kyung [5 ]
Choi, Kevin Kinam [6 ]
Cha, Yong-Won [6 ]
Choi, Changhwan [7 ]
机构：
[1] Inha Univ, Dept Mat Sci & Engn, Incheon 402751, South Korea
[2] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea
[3] Sungkyunkwan Univ, Sch Adv Mat Sci & Engn, Suwon 16419, South Korea
[4] Inha Univ, Dept Phys, Incheon 402751, South Korea
[5] Natl NanoFab Ctr NNFC, Daejon 34141, South Korea
[6] The Bondis, Hwaseong 18449, South Korea
[7] Hanyang Univ, Div Mat Sci & Engn, Seoul 04763, South Korea
来源：
2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2016年
基金：
新加坡国家研究基金会;
关键词：
Monolithic; 3D; Low Temperature Bonding; Epitaxial Growth; Gate Stack; Laser Annealing;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (<450 degrees C), low temperature (<550 degrees C) in-situ doped S/D selective SiGe epi process, low temperature (<200 degrees C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.
引用
收藏
页数：2
相关论文
共 50 条
  • [21] Low Temperature Wafer Bonding for Wafer-Level 3D Integration
    Dragoi, V.
    Rebhan, B.
    Burggraf, J.
    Razek, N.
    2014 4TH IEEE INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D), 2014, : 9 - 9
  • [22] 3D monolithic integration
    Batude, P.
    Vinet, M.
    Pouydebasque, A.
    Le Royer, C.
    Previtali, B.
    Tabone, C.
    Hartmann, J. -M.
    Sanchez, L.
    Baud, L.
    Carron, V.
    Toffoli, A.
    Allain, F.
    Mazzocchi, V.
    Lafond, D.
    Deleonibus, S.
    Faynot, O.
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 2233 - 2236
  • [23] Monolithic 3D Integration Process and Its Device Applications
    Choi, Changhwan
    6TH IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2022), 2022, : 76 - 78
  • [24] Sequential 3D Process Integration: Opportunities For Low Temperature Processing
    Kerdiles, S.
    Acosta-Alba, P.
    Mathieu, B.
    Veillerot, M.
    Denis, H.
    Aussenac, F.
    Mazzamuto, F.
    Toque-Tresonne, I.
    Huet, K.
    Samson, M-P.
    Previtali, B.
    Brunet, L.
    Batude, P.
    Fenouillet-Beranger, C.
    SEMICONDUCTOR PROCESS INTEGRATION 10, 2017, 80 (04): : 215 - 225
  • [25] Development and Electrical Performance of Low Temperature Cu-Sn/In Bonding for 3D Flexible Substate Integration
    Hu, Yu-Chen
    Chen, Kuan-Neng
    2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), 2016, : 164 - 165
  • [26] 3D Interconnection Process Development and Integration with Low Stress TSV
    Chua, T. T.
    Ho, S. W.
    Li, H. Y.
    Khong, C. H.
    Liao, E. B.
    Chew, S. P.
    Lee, W. S.
    Lim, L. S.
    Pang, X. F.
    Kriangsak, S. L.
    Ng, C.
    Nathapong, S.
    Toh, C. H.
    2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 798 - 802
  • [27] Cu passivation for enhanced low temperature (≤300 °C) bonding in 3D integration
    Lim, D. F.
    Wei, J.
    Leong, K. C.
    Tan, C. S.
    MICROELECTRONIC ENGINEERING, 2013, 106 : 144 - 148
  • [28] Research of Electroplating and Electroless Plating for Low Temperature Bonding in 3D Heterogeneous Integration
    Hu, Yu-Chen
    Chang, Yao-Jen
    Wu, Chun-Shen
    Cheng, Yung Mao
    Chen, Wei Jen
    Chen, Kuan-Neng
    2014 9TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2014, : 290 - 293
  • [29] Recent advances in low temperature process In view of 3D VLSI integration
    Fenouillet-Beranger, C.
    Batude, P.
    Brunet, L.
    Mazzocchi, V.
    Lu, C-M. V.
    Deprat, F.
    Micout, J.
    Samson, M-P.
    Previtali, B.
    Besombes, P.
    Rambal, N.
    Lapras, V.
    Andrieu, F.
    Billoint, O.
    Brocard, M.
    Thuries, S.
    Cibrario, G.
    Acosta-Alba, P.
    Mathieu, B.
    Kerdiles, S.
    Nemouchi, F.
    Arvet, C.
    Besson, P.
    Loup, V.
    Gassilloud, R.
    Garros, X.
    Leroux, C.
    Beugin, V.
    Guerin, C.
    Benoit, D.
    Pasini, L.
    Hartmann, J-M.
    Vinet, M.
    2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2016,
  • [30] Low Temperature Wafer Bonding for 3D Applications
    Burggraf, J.
    Bravin, J.
    Wiesbauer, H.
    Dragoi, V.
    PROCESSING, MATERIALS, AND INTEGRATION OF DAMASCENE AND 3D INTERCONNECTS 5, 2014, 58 (17): : 67 - 73
12345