3D monolithic integration

被引：0
|
作者：
Batude, P. [1 ]
Vinet, M. [1 ]
Pouydebasque, A. [1 ]
Le Royer, C. [1 ]
Previtali, B. [1 ]
Tabone, C. [1 ]
Hartmann, J. -M. [1 ]
Sanchez, L. [1 ]
Baud, L. [1 ]
Carron, V. [1 ]
Toffoli, A. [1 ]
Allain, F. [1 ]
Mazzocchi, V. [1 ]
Lafond, D. [1 ]
Deleonibus, S. [1 ]
Faynot, O. [1 ]
机构：
[1] CEA Leti, Minatec, Grenoble, France
来源：
2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2011年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
3D monolithic integration, thanks to its high vertical density of interconnections, is the only available option for applications requiring connections at the transistor scale. However to achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low thermal budget top FET still have to be solved. In this work, a 3D monolithic process flow relying on molecular wafer bonding is proposed and results in all critical steps are given. Significant breakthroughs have been obtained using a full wafer molecular bonding with thin interlayer dielectric and an original salicidation process stabilized up to 650 degrees C enabling to reach high performance for the top and bottom transistor. With such technology, we demonstrate functional top and bottom transistors as well as 3D structures such as invertors and SRAMs.
引用
收藏
页码：2233 / 2236
页数：4
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