Direct Bonding: a Key Enabler for 3D Monolithic Integration

被引：14
|
作者：
Brunet, L. [1 ]
Batude, P. [1 ]
Fournel, F. [1 ]
Benaissa, L. [1 ]
Fenouillet-Beranger, C. [1 ]
Pasini, L. [2 ]
Deprat, F. [1 ]
Previtali, B. [1 ]
Ponthenier, F. [1 ]
Seignard, A. [1 ]
Euvrard-Colnat, C. [1 ]
Rivoire, M. [2 ]
Besson, P. [2 ]
Arvet, C. [2 ]
Beche, E. [1 ]
Rozeau, O. [1 ]
Billoint, O. [1 ]
Turkyilmaz, O. [1 ]
Clermidy, F. [1 ]
Signamarcheix, T. [1 ]
Vinet, M. [1 ]
机构：
[1] CEA LETI MINATEC Campus, F-38054 Grenoble, France
[2] STMicroelectronics, F-38920 Crolles, France
来源：
SEMICONDUCTOR WAFER BONDING 13: SCIENCE, TECHNOLOGY, AND APPLICATIONS | 2014年 / 64卷 / 05期
关键词：
SEQUENTIAL INTEGRATION;
D O I：
10.1149/06405.0381ecst
中图分类号：
O646 [电化学、电解、磁化学];
学科分类号：
081704 ;
摘要：
By stacking transistor levels on each other sequentially, monolithic 3D integration appears to be an alternative solution to scaling. By taking fully advantages of the vertical dimension, circuit partitioning at the transistor scale is then possible. This paper reviews the different opportunities offered by such technology and summarizes the technological challenges related to this integration. A general overview of the different techniques to create an active layer above a bottom transistor level is presented. Direct bonding from a SOI wafer clearly appears to be currently the best solution to obtain a defect free monocrystalline active layer with a well-controlled thickness. Finally, the challenge of realizing a top transistor level with a low temperature thermal budget is explained. This thermal budget is quantified by studying the electrical stability of the bottom level. Some electrical results on low temperature activated junctions are also presented.
引用
收藏
页码：381 / 390
页数：10
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