Design of 4:2 Energy-Efficient Compressor Using Hybrid 1-bit Full Adder

被引：0

作者：

Singh, Anil ^{[1
]}

Kumar, Manish ^{[1
]}

机构：

[1] Madan Mohan Malaviya Univ Technol, Dept ECE, Gorakhpur, Uttar Pradesh, India

来源：

JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES | 2020年 / 15卷 / 1-2期

关键词：

Power dissipation; delay; power-delay product; 1-bit full adder; CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper present an energy-efficient 4:2 compressor by utilizing hybrid 1-bit full adder which results in low power dissipation and less delay. The proposed circuit also uses only 28 transistors which results in enhancement in its performance. The proposed 4:2 compressor has power dissipation 909.22 pW and delay of 11.60 pS at 1.0V power supply whereas power dissipation of 18.29 nW and delay 1.73 pS

引用

页码：9 / 12

页数：4

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