Analog Performance of Bulk Planar Junctionless Transistor (BPJLT)

被引:0
|
作者
Baruah, Ratul Kumar [1 ]
Paily, Roy P. [1 ]
机构
[1] IIT Guwahati, Dept Elect & Elect Engn, Gauhati, India
关键词
Analog Behaviour; BPJLT; Junctionless transistor (JLT); scaling; SOI;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, analog performance of bulk planer junctionless transistor (BPJLT) is reported for the first time. The analog performance parameters, namely transconductance/drain current ratio (G(m)/I-D), intrinsic gain (G(m)R(o)) and unity gain frequency (f(T)) for n-type BPJLT are systematically investigated with the help of extensive device simulations. The results are then compared with silicon on insulator junctionless transistor (SOI JLT). BPJLT is found to have significantly overall better performance as compared to SOI JLT in regard of analog behaviour.
引用
收藏
页数:4
相关论文
共 50 条
  • [1] Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling
    Gundapaneni, Suresh
    Ganguly, Swaroop
    Kottantharayil, Anil
    IEEE ELECTRON DEVICE LETTERS, 2011, 32 (03) : 261 - 263
  • [2] Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors
    Ghosh, Bahniman
    Khan, Uzma
    Tripathi, Ball Mukund Mani
    Akram, M. W.
    JOURNAL OF LOW POWER ELECTRONICS, 2013, 9 (04) : 490 - 495
  • [3] A Novel Bulk Planar Junctionless Field-Effect Transistor for High-Performance Biosensing
    Son, Jeongmin
    Heo, Chan
    Kim, Hyeongyu
    Meyyappan, M.
    Kim, Kihyun
    BIOSENSORS-BASEL, 2025, 15 (03):
  • [4] Negative capacitance δ-bulk planar junctionless transistor for low power applications
    Bhagat, Khemnand B.
    Patil, Ganesh C.
    MICRO & NANO LETTERS, 2019, 14 (10) : 1107 - 1110
  • [5] Analog performance investigation of misaligned double gate junctionless transistor
    S. Intekhab Amin
    R. K. Sarin
    Journal of Computational Electronics, 2015, 14 : 675 - 685
  • [6] Analog performance investigation of misaligned double gate junctionless transistor
    Amin, S. Intekhab
    Sarin, R. K.
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2015, 14 (03) : 675 - 685
  • [7] Impact of Pocket Doping On the Performance of Planar SOI Junctionless Transistor
    Faisal Bashir
    Asim M. Murshid
    Farooq A. Khanday
    Mohammad Tariq Banday
    Silicon, 2021, 13 : 1771 - 1776
  • [8] Impact of Pocket Doping On the Performance of Planar SOI Junctionless Transistor
    Bashir, Faisal
    Murshid, Asim M.
    Khanday, Farooq A.
    Banday, Mohammad Tariq
    SILICON, 2021, 13 (06) : 1771 - 1776
  • [9] Engineering substrate doping in bulk planar junctionless transistor: Scalability and variability study
    Bhagat, Khemnand
    Patil, Ganesh C.
    ENGINEERING RESEARCH EXPRESS, 2020, 2 (02):
  • [10] Impact of Doping and Spacer on the Performance of Bulk Planar Junctionless devices
    Scarlet, S. Priscilla
    Srinivasan, R.
    2018 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENERGY SYSTEMS (ICEES), 2018, : 267 - 273