Analog performance investigation of misaligned double gate junctionless transistor

In this paper, the analog performance of a misaligned double gate junctionless transistor (DGJLT) is demonstrated for the first time. The gate misalignment can occur on either source side (MA_S) or at drain side (MA_D). Since misalignment is a type of degradation that occurs during device fabrication, the idea behind this demonstration is to analyze the impact of gate misalignment on DGJLT. The analog performance parameters analyzed are, transconductance (g(m)), output conductance (g(ds)), early voltage (V-EA) and intrinsic gain (A(VO)). They are compared with a double gate inversion mode transistor (DGIMT) under same gate misalignment condition. A DGJLT is found to have better tolerance to gate misalignment compared to DGIMT. MA_S configuration of a DGJLT shows better analog performance compared to MA_D configuration where as for DGIMT it shows better performance for MA_D compared to MA_S configuration.