FPGA Implementation of Hybrid Han-Carlson Adder

被引：0
|
作者：
Gedam, Swapna [1 ]
Zode, Pravin [1 ]
Zode, Pradnya [1 ]
机构：
[1] YC Coll Engn, Dept Elect Engn, Nagpur 441110, Maharashtra, India
来源：
2014 2ND INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS) | 2014年
关键词：
Parallel Prefix Adders; Han-Carlson adder; Hybrid Han-Carlson Adder; prefix computation;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper a modified parallel prefix adder, Hybrid Han-Carlson adder is proposed which uses different stages of Brent-Kung and Kogge-Stone adders. Binary addition is one of the primitive and most commonly used application in computer arithmetic. Parallel prefix adders offer a highly efficient solution to the binary addition problem and are well suited for FPGA implementation. Carry propagation in binary addition can be efficiently expressed as a prefix computation. Modified Hybrid Han-Carlson adder reduces the complexity, area and power consumption significantly.
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页数：4
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