FPGA Implementation of Hybrid Han-Carlson Adder

被引：0
|
作者：
Gedam, Swapna [1 ]
Zode, Pravin [1 ]
Zode, Pradnya [1 ]
机构：
[1] YC Coll Engn, Dept Elect Engn, Nagpur 441110, Maharashtra, India
来源：
2014 2ND INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS) | 2014年
关键词：
Parallel Prefix Adders; Han-Carlson adder; Hybrid Han-Carlson Adder; prefix computation;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper a modified parallel prefix adder, Hybrid Han-Carlson adder is proposed which uses different stages of Brent-Kung and Kogge-Stone adders. Binary addition is one of the primitive and most commonly used application in computer arithmetic. Parallel prefix adders offer a highly efficient solution to the binary addition problem and are well suited for FPGA implementation. Carry propagation in binary addition can be efficiently expressed as a prefix computation. Modified Hybrid Han-Carlson adder reduces the complexity, area and power consumption significantly.
引用
收藏
页数：4
相关论文
共 50 条
  • [41] A Fast FPGA-Based BCD Adder
    Mubin Ul Haque
    Zarrin Tasnim Sworna
    Hafiz Md. Hasan Babu
    Ashis Kumer Biswas
    Circuits, Systems, and Signal Processing, 2018, 37 : 4384 - 4408
  • [42] Improved Redundant Binary Adder Realization in FPGA
    Sahu, Satya Ranjan
    Bhoi, Bandan Kumar
    Pradhan, Manoranjan
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2021, 30 (16)
  • [43] A new floating-point adder FPGA-based implementation using RN-coding of numbers
    Araujo, Tulio
    Cardoso, Matheus B. R.
    Nepomuceno, Erivelton G.
    Llanos, Carlos H.
    Arias-Garcia, Janier
    COMPUTERS & ELECTRICAL ENGINEERING, 2021, 90
  • [44] Design and implementation of high-performance 20-T hybrid full adder circuit
    Kandpal, Jyoti
    Tomar, Abhishek
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2024, 119 (01) : 97 - 110
  • [45] FPGA implementation of high-fidelity hybrid reversible watermarking algorithm
    Das, Subhajit
    Sunaniya, A. K.
    MICROPROCESSORS AND MICROSYSTEMS, 2022, 89
  • [46] IMPLEMENTATION ANALYSIS FOR A HYBRID PARTICLE FILTER ON AN FPGA BASED SMART CAMERA
    Zurianain, I.
    Arana, N.
    Lerasle, F.
    VISAPP 2010: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON COMPUTER VISION THEORY AND APPLICATIONS, VOL 1, 2010, : 174 - 179
  • [47] Implementation and Evaluation of Distributed Processing on a PC-FPGA Hybrid System
    Takano K.
    Oda T.
    Ozaki R.
    Uejima A.
    Kohata M.
    IEEJ Transactions on Electronics, Information and Systems, 2022, 142 (11) : 1199 - 1207
  • [48] Implementation of Distributed Processing Using a PC-FPGA Hybrid System
    Takano, Keisuke
    Oda, Tetsuya
    Ozaki, Ryo
    Uejima, Akira
    Kohata, Masaki
    2019 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT 2019), 2019, : 387 - 390
  • [49] FPGA Implementation and Evaluation of two Cryptographically Secure Hybrid Cellular Automata
    Ioana, Dogaru
    Radu, Dogaru
    2014 10TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS (COMM), 2014,
  • [50] FPGA Implementation of a Hybrid Sensorless Control of SMPMSM in the Whole Speed Range
    Ma, Zhixun
    Gao, Jianbo
    Kennel, Ralph
    IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, 2013, 9 (03) : 1253 - 1261
12345