A CMOS Track-and-Hold Circuit with beyond 30 GHz Input Bandwith

被引：0
|
作者：
Sedighi, Behnam [1 ]
Huynh, Anh T. [1 ]
Skafidas, Efstratios [1 ]
机构：
[1] Univ Melbourne, Natl ICT Australia, Dept Elect & Elect Engn, Melbourne, Vic 3010, Australia
来源：
2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS) | 2012年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
To realize future ultra high-speed data converters, sampling circuits with very large bandwidth are required. This paper studies the design of ultra high-speed Track-and-Hold (T/H) circuits. A bootstrapping circuit for T/H is presented. The proposed T/H is simulated in 32 nm SOI-CMOS technology. It achieves an input bandwidth higher than 30 GHz and provides an SNDR higher than 43.8 dB (ENOB > 7.0 b) when sampling a 34 GHz input signal at 10 GS/s.
引用
收藏
页码：113 / 116
页数：4
相关论文
共 50 条
  • [41] HIGH-SPEED BICMOS CURRENT-MODE DIFFERENTIAL TRACK-AND-HOLD CIRCUIT
    REIMANN, T
    KRUMMENACHER, F
    DECLERCQ, M
    [J]. ELECTRONICS LETTERS, 1994, 30 (21) : 1730 - 1732
  • [42] High-speed CMOS Track/Hold circuit design
    Kobayashi, H
    Zin, MAM
    Kobayashi, K
    San, H
    Sato, H
    Ichimura, JI
    Onaya, Y
    Kurosawa, N
    Kimura, Y
    Yuminaka, Y
    Tanaka, K
    Myono, T
    Abe, F
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2001, 27 (1-2) : 161 - 170
  • [43] High-Speed CMOS Track/Hold Circuit Design
    Haruo Kobayashi
    Mohd Asmawi Mohamed Zin
    Kazuya Kobayashi
    Hao San
    Hiroyuki Sato
    Jun-Ichi Ichimura
    Yoshitaka Onaya
    Yuuichi Takahashi
    Naoki Kurosawa
    Yasuyuki Kimura
    Yasushi Yuminaka
    Kouji Tanaka
    Takao Myono
    Fuminori Abe
    [J]. Analog Integrated Circuits and Signal Processing, 2001, 27 : 161 - 170
  • [44] A 4 GSa/s, 16-GHz Input bandwidth Master-Slave Track-and-Hold Amplifier in InP DHBT technology
    Deza, J.
    Ouslimani, A.
    Konczykowska, A.
    Kasbari, A.
    Godin, J.
    [J]. 2012 20TH TELECOMMUNICATIONS FORUM (TELFOR), 2012, : 502 - 505
  • [45] A 1.8 V 10-bit 80 MS/s low power track-and-hold circuit in a 0.18 μm CMOS process
    Säll, E
    [J]. PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING, 2003, : 53 - 56
  • [46] 70 GSa/s and 51 GHz bandwidth track-and-hold amplifier in InP DHBT process
    Deza, J.
    Ouslimani, A.
    Konczykowska, A.
    Kasbari, A.
    Godin, J.
    Pailler, G.
    [J]. ELECTRONICS LETTERS, 2013, 49 (06) : 388 - 389
  • [47] Low distortion input buffer for high resolution GS/s rate track-and-hold amplifiers
    Avitabile, G.
    Cascella, D.
    Cannone, F.
    Coviello, G.
    [J]. ELECTRONICS LETTERS, 2012, 48 (13) : 755 - 757
  • [48] A 35-GHz Bandwidth 30 GSa/s InP Track-and-Hold Amplifier Using Enhanced fT-Doubler Technique
    Zhen, Wenxiang
    Xiao, Luning
    Cao, Shurui
    Su, Yongbo
    Jin, Zhi
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (11) : 4243 - 4247
  • [49] Differentially pre-compensated GHz-range low-voltage track-and-hold
    Tchamov, N
    Velichkov, M
    Keränen, A
    Stoyanov, V
    [J]. ELECTRONICS LETTERS, 2003, 39 (02) : 180 - 180
  • [50] A 1-GSample/s, 15-GHz Input Bandwidth Master-Slave Track-and-Hold Amplifier in InP DHBT Technology
    Bouvier, Yves
    Ouslimani, Achour
    Konczykowska, Agnieszka
    Godin, Jean
    [J]. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2009, 57 (12) : 3181 - 3187
12345