High-Speed CMOS Track/Hold Circuit Design

被引：0
|
作者：
Haruo Kobayashi
Mohd Asmawi Mohamed Zin
Kazuya Kobayashi
Hao San
Hiroyuki Sato
Jun-Ichi Ichimura
Yoshitaka Onaya
Yuuichi Takahashi
Naoki Kurosawa
Yasuyuki Kimura
Yasushi Yuminaka
Kouji Tanaka
Takao Myono
Fuminori Abe
机构：
[1] Gunma University,Department of Electronic Engineering
[2] Sanyo Electric Corp.,Semiconductor Company
来源：
Analog Integrated Circuits and Signal Processing | 2001年 / 27卷
关键词：
Track/Hold circuit; Sample/Hold circuit; AD converter; sampling; CMOS;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This paper describes the design of a high-speed CMOSTrack/Hold circuit in front of an ADC. The Track/Hold circuit employsdifferential open-loop architecture, very linear source follower inputbuffers, NMOS sampling switches and bootstrap sampling-switch drivercircuits for high-speed operation with 3.3 V supply voltage. SPICEsimulations with MOSIS 0.35 μm CMOS BSIM3v3 parameters showed thatit achieves a signal-to-(noise+distortion)-ratio (SNDR) of morethan 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mWpower consumption.
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页码：161 / 170
页数：9
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