A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array

被引:9
|
作者
Hsiao, SF [1 ]
Shiue, WR [1 ]
机构
[1] Natl Sun Yat Sen Univ, Dept Comp Sci & Engn, Taipei, Taiwan
关键词
DCT; image compression; linear array; multimedia processing;
D O I
10.1109/76.964780
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new recursive algorithm with hardware complexity of O (log(2)N) is derived for fast computation of N x N 2-D discrete cosine transforms (2-D DCTs). It first converts the original 2-D data matrices into 1-D vectors and then employs different partition methods for the input and output indices in the 1-D vector space. Afterward, the algorithm computes the corresponding;2-D complex DCT (2-D CCT) and then uses a post-addition step to produce simultaneously two 2-D DCT outputs. The decomposed form of the 2-D recursive algorithm looks like a radix-4 fast Fourier transform algorithm. The common entries in each row of the butterfly-like matrix are factored out in order to reduce the number of multipliers needed during implementation. A new linear architecture for the derived algorithm is presented which leads to a hardware-efficient architectural design requiring only log, N complex multipliers plus 3log(2)N complex adders/subtractors for the computation of a 2-D N x N CCT.
引用
收藏
页码:1149 / 1159
页数:11
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