Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices

Low power hardware acceleration cores for integration into real-time High Efficiency Video Coding (HEVC) codec for smartphones, tablets, camcorders, and televisions are in great demand. This need motivates one for an efficient realization of Discrete Cosine Transform (DCT) and Inverse-DCT (IDCT) for HEVC. This paper presents an algorithm to calculate the required minimum number of low-frequency DCT-output/IDCT-input coefficients for 4, 8, 16, and 32-point DCT/IDCT in HEVC, such that there is a slight decrease in peak-signal-to-noise-ratio (<0.15 decibel) and a minor increment in bitrate (<1.5%) as compared to the reference HEVC-Test-Model (HM) Software. However, the encoding time gets reduced at most by 17.95% for Class-A type sequences, while reporting mean-squared-error and structural-similarity of 1.42 and 0.9913, respectively for 4K ultra-high-definition videos. Moreover, HEVC-compliant computationally efficient architectures are introduced for n-point DCT/IDCT. The presented flexible Transpose Memory architecture uses only sixteen random-access-memories to support all transform-unit sizes in HEVC. The proposed two-dimensional DCT/IDCT architecture can process up to 288@4K frames-per-second, and it consumes the minimum power, energy, and area of 11.23 milliwatts, 2.34 picojoules, and 120 kilo-gate-equivalents, respectively. Such design with low power, area, and energy features can be included in a real-time HEVC codec for HEVC-compliant consumer electronic devices.