Study on Interconnect Test with Multiple Scan Chains Based on VXIbus Boundary Scan Module

被引：0
|
作者：
Yin Xianhua [1 ]
Zhu Wangchun [1 ]
Mo Taiping [1 ]
机构：
[1] Guilin Univ Elect Technol, Elect Engineer Sch, Guilin 541004, Peoples R China
来源：
PROCEEDINGS OF THE SECOND INTERNATIONAL SYMPOSIUM ON TEST AUTOMATION & INSTRUMENTATION, VOLS 1-2 | 2008年
关键词：
boundary scan; multiple scan chains; interconnect test;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The use of multiple scan chains for interconnect test is analyzed. Based on the researches on greedy strategy for configuring multiple scan chains for internal test and the sorting algorithm of single scan chain for Cluster test, a solution of configuring and optimizing multiple scan chains for interconnect test is presented. It will aim to decrease the test time and increase the efficiency and reliability for interconnect test: significantly. Experiment results show that the expected design objective is achieved.
引用
收藏
页码：119 / 123
页数：5
相关论文
共 50 条
  • [21] On the coverage of delay faults in scan designs with multiple scan chains
    Pomeranz, I
    Reddy, SM
    ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 2002, : 206 - 209
  • [22] Boundary scan: The Internet of test
    Wondolowski, M
    Bennetts, B
    Ley, A
    IEEE DESIGN & TEST OF COMPUTERS, 1999, 16 (03): : 34 - 43
  • [23] Boundary scan test standards
    Ashenden, PJ
    IEEE DESIGN & TEST OF COMPUTERS, 2003, 20 (01): : 91 - 92
  • [24] Boundary scan test in practice
    Australian Electronics Engineering, 1992, 24 (04):
  • [25] Parallel core testing with multiple scan chains by test vector overlapping
    Shinogi, T
    Yamada, Y
    Hayashi, T
    Yoshikawa, T
    Tsuruoka, S
    2005 IEEE VLSI-TSA INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION & TEST (VLSI-TSA-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 204 - 207
  • [26] On interconnecting circuits with multiple scan chains for improved test data compression
    Pomeranz, I
    Reddy, SM
    17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 741 - 744
  • [27] Low power test compression technique for designs with multiple scan chains
    Shi, YH
    Togawa, N
    Kimura, S
    Yanagisawa, M
    Ohtsuki, T
    14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 386 - 389
  • [28] Design of boundary scan master based on PCB test
    Zhang, SJ
    Lan, ZW
    ICEMI 2005: CONFERENCE PROCEEDINGS OF THE SEVENTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOL 2, 2005, : 57 - 59
  • [29] At-speed boundary-scan interconnect testing in a board with multiple system clocks
    Shin, J
    Kim, H
    Kang, S
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 473 - 477
  • [30] The study on boundary scan test in mixed circuit system
    Peng, XY
    Peng, Y
    Qiao, LY
    ICEMI'2001: FIFTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT AND INSTRUMENTS, VOL 1, CONFERENCE PROCEEDINGS, 2001, : 455 - 458
12345