A Modified ESD Clamp Circuit for 90-nm CMOS Process

被引：0

作者：

Liu, Hong-Xia ^{[1
]}

Yang, Zhao-Nian ^{[1
]}

Luo, Yi ^{[2
]}

Liu, Chen ^{[2
]}

机构：

[1] Xidian Univ, Sch Microelect, Key Lab, Minist Educ Wide Band Gap Semicond Mat & Devices, Xian 710071, Peoples R China

[2] Xian Semipower Elect Technol Co, Xian 710075, Peoples R China

来源：

2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012) | 2012年

基金：

中国国家自然科学基金;

关键词：

DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In nanoscale CMOS process, integrated circuits (ICs) face serious gate reliability issues such as the damage of electrostatic discharge (ESD). The RC-triggered silicon-controlled rectifier (SCR) is widely studied for the high turn-on efficiency and discharge capability. However, the large gate leakage current of MOS capacitor in the traditional RC network in nanoscale process is not desired. In this work, a modified detection circuit with feedback technique is proposed. The leakage current is reduced to 16 nA at room temperature (25 degrees C). Under the ESD event, it injects 38 mA trigger current into the p-substrate of SCR. Compared with the previous circuits, the proposed circuit can save area and power consumption while achieving the same performance. The simulation result shows that this clamp circuit can be used in industry.

引用

页码：872 / 875

页数：4

共 50 条

[1] A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process
Yang Zhaonian
Liu Hongxia
Wang Shulong
JOURNAL OF SEMICONDUCTORS, 2013, 34 (04)
[2] A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process
杨兆年
刘红侠
王树龙
JournalofSemiconductors, 2013, 34 (04) : 116 - 120
[3] ESD Detection Circuit with Reverse-used RC Network in a 90-nm CMOS Process
Yang, Z. N.
Liu, H. X.
Wang, S. L.
PROCEEDINGS OF THE 2013 20TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2013), 2013, : 583 - 586
[4] 2xVDD-Tolerant ESD Detection Circuit in a 90-nm Low-Voltage CMOS Process
Yang, Zhaonian
Zhang, Yue
Yu, Ningmei
Liou, Juin J.
2018 7TH IEEE INTERNATIONAL SYMPOSIUM ON NEXT-GENERATION ELECTRONICS (ISNE), 2018, : 48 - 51
[5] 5 GS/s Track and Hold Circuit in 90-nm CMOS Technology Process
dela Cerna Lowaton, Allenn
Auguis, Daryl S.
2015 INTERNATIONAL CONFERENCE ON HUMANOID, NANOTECHNOLOGY, INFORMATION TECHNOLOGY,COMMUNICATION AND CONTROL, ENVIRONMENT AND MANAGEMENT (HNICEM), 2015, : 492 - +
[6] Statically triggered 3 x VDD-Tolerant ESD detection circuit in a 90-nm low-voltage CMOS process
Yang, Zhaonian
Yang, Yuan
Yu, Ningmei
Liou, Juin J.
MICROELECTRONICS JOURNAL, 2018, 78 : 88 - 93
[7] 3×VDD-tolerant ESD detection circuit in a 90 nm CMOS process
Yang, Zhaonian
Liu, Hongxia
Zhu, Jia
Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University, 2015, 42 (01): : 56 - 61
[8] A 40-Gb/s decision circuit in 90-nm CMOS
Chalvatzis, T.
Yau, K. H. K.
Schvan, P.
Yang, M. T.
Voinigescu, S. P.
ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2006, : 512 - +
[9] Design of a Quadrature Clock Conditioning Circuit in 90-nm CMOS Technology
Zaki, Tarek
Ferenci, Damir
Groezing, Markus
Berroth, Manfred
2008 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2008, : 425 - 428
[10] 90-nm process technology
不详
AMERICAN CERAMIC SOCIETY BULLETIN, 2002, 81 (12): : 16 - 16

← 1 2 3 4 5 →