Design of a Quadrature Clock Conditioning Circuit in 90-nm CMOS Technology

被引：0

作者：

Zaki, Tarek ^{[1
]}

Ferenci, Damir ^{[1
]}

Groezing, Markus ^{[1
]}

Berroth, Manfred ^{[1
]}

机构：

[1] Univ Stuttgart, Inst Elect & Opt Commun Engn, Stuttgart, Germany

来源：

2008 INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2008年

关键词：

Clocks; CMOS Integrated Circuits; Duty-Cycle Control; Feedback Circuits; Phase Control;

D O I：

10.1109/ICM.2008.5393511

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the operation and problems of the conventional clock conditioning circuits. A modified design is proposed to eliminate these problems and to merge two conditioning circuits together. This is to adjust and maintain two output signal properties actively during circuit operation for 4-phase 10 GHz single-ended clock signals. It is desired to have an exact 50% duty-cycle for each signal and a 90 degrees phase difference between them. Simulation results in 90-nm CMOS technology are provided showing low output jitter.

引用

页码：425 / 428

页数：4

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