Predicting the performance of a 3D processor-memory chip stack

被引：32

作者：

Jacob, P ^{[1
]}

Erdogan, O ^{[1
]}

Zia, A ^{[1
]}

Belemjian, PM ^{[1
]}

Kraft, RP ^{[1
]}

McDonald, JF ^{[1
]}

机构：

[1] Rensselaer Polytech Inst, Dept Elect Comp & Syst Engn, Ctr Integrated Elect, Troy, NY 12181 USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2005年 / 22卷 / 06期

关键词：

D O I：

10.1109/MDT.2005.151

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A primary bottleneck in the performance of a processor is in its communication with memory. By allowing the placement of processor and memory in adjacent layers, 3D design provides significant relief, reducing the communication latency. This article studies the impact of 3D design by comparing the cycles per instruction of such a design with various alternatives. © 2005 IEEE.

引用

下载

页码：540 / 547

页数：8

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