Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs

被引：68
|
作者：
Karmakar, Supriya [1 ,2 ]
Chandy, John A. [1 ]
Jain, Faquir C. [1 ]
机构：
[1] Univ Connecticut, Dept Elect & Comp Engn, Storrs, CT 06269 USA
[2] Intel Corp, Hillsboro, OR 97124 USA
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2013年 / 21卷 / 05期
关键词：
Integrated circuit; quantum dot gate field effect transistor (QDGFET); ternary logic; VLSI; NEGATIVE DIFFERENTIAL RESISTANCE; RESONANT-TUNNELING TRANSISTOR; PERFORMANCE; FABRICATION; MODFET; HEMT; WELL;
D O I：
10.1109/TVLSI.2012.2198248
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we discuss logic circuit designs using the circuit model of three-state quantum dot gate field effect transistors (QDGFETs). QDGFETs produce one intermediate state between the two normal stable ON and OFF states due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Interesting logic can be implemented using QDGFETs. In this paper, we discuss the designs of various two-input three-state QDGFET gates, including NAND- and NOR-like operations and their application in different combinational circuits like decoder, multiplier, adder, and so on. Increased number of states in three-state QDGFETs will increase the number of bit-handling capability of this device and will help us to handle more number of bits at a time with less circuit elements.
引用
收藏
页码：793 / 806
页数：14
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