A review on the design of ternary logic circuits*

被引：11

作者：

Wang, Xiao-Yuan ^{[1
]}

Dong, Chuan-Tao ^{[1
]}

Wu, Zhi-Ru ^{[1
]}

Cheng, Zhi-Qun ^{[1
]}

机构：

[1] Hangzhou Dianzi Univ, Sch Elect & Informat, Hangzhou 310018, Peoples R China

来源：

CHINESE PHYSICS B | 2021年 / 30卷 / 12期

基金：

中国国家自然科学基金;

关键词：

ternary logic circuit; memristor; digital logic circuit; circuit design; MULTIPLE-VALUED LOGIC; LOW-POWER; ENERGY-EFFICIENT; HIGH-PERFORMANCE; FULL ADDER; FLIP-FLOP; CNFET; CMOS; VOLTAGE; GATES;

D O I：

10.1088/1674-1056/ac248b

中图分类号：

O4 [物理学];

学科分类号：

0702 ;

摘要：

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity, power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

引用

页数：12

共 50 条

[1] A review on the design of ternary logic circuits
王晓媛
董传涛
吴志茹
程知群
Chinese Physics B, 2021, 30 (12) : 691 - 702
[2] Design of Encoder for Ternary Logic Circuits
Saidutt, Viswa P.
Srinivas, V
Phaneendra, Sai P.
Muthukrishnan, Moorthy N.
2012 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS & ELECTRONICS (PRIMEASIA), 2012, : 85 - 88
[3] Design Methodologies for Ternary Logic Circuits
Vudadha, Chetan
Srinivas, M. B.
2018 IEEE 48TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2018), 2018, : 192 - 197
[4] Design of Ternary Logic Circuits using CNTFET
Prasad, Vikash
Banerjee, Anirban
Das, Debaprasad
2018 INTERNATIONAL SYMPOSIUM ON DEVICES, CIRCUITS AND SYSTEMS (ISDCS), 2018,
[5] A Review on Fundamentals of Ternary Reversible Logic Circuits
Rani, P. Mercy Nesa
Thangkhiew, Phrangboklang Lyngton
2020 INTERNATIONAL CONFERENCE ON COMPUTATIONAL PERFORMANCE EVALUATION (COMPE-2020), 2020, : 738 - 743
[6] Design of Ternary Logic Circuits Using GNRFET and RRAM
Shaik Javid Basha
P. Venkatramana
Circuits, Systems, and Signal Processing, 2023, 42 : 7335 - 7356
[7] Design And Novel Approach For Ternary And Quaternary Logic Circuits
Mahesh, R. N. Uma
Sudeep, J.
2017 2ND INTERNATIONAL CONFERENCE FOR CONVERGENCE IN TECHNOLOGY (I2CT), 2017, : 1224 - 1227
[8] Design of Ternary Logic Circuits Using GNRFET and RRAM
Basha, Shaik Javid
Venkatramana, P.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2023, 42 (12) : 7335 - 7356
[9] Design of Ternary Logic and Arithmetic Circuits Using GNRFET
Sandhie, Zarin Tasnim
Ahmed, Farid Uddin
Chowdhury, Masud H.
IEEE OPEN JOURNAL OF NANOTECHNOLOGY, 2020, 1 : 77 - 87
[10] An Optimal Gate Design for the Synthesis of Ternary Logic Circuits
Kim, Sunmean
Lim, Taeho
Kang, Seokhyeong
2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2018, : 476 - 481

← 1 2 3 4 5 →