Inherent Reliability Evaluation of Networks-on-Chip Based on Analytical Models

被引：0
|
作者：
Valinataj, Mojtaba [1 ]
Mohammadi, Siamak [1 ]
Safari, Saeed [1 ]
机构：
[1] Univ Tehran, Dept Elect & Comp Engn, Tehran, Iran
来源：
2008 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS | 2008年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Reliability evaluation based on analytical models is a precise method for dependability analysis before and after designing the fault-tolerant systems. In this paper, we present the precise formulations for the inherent reliability of mesh-based NoCs that also depend on the employed routing algorithm and traffic model. Based on this analysis, the effects of some permanent failures in the links, switches or cores on the packet delivery of NoCs are determined. The models can be extended to evaluate the fault-tolerant methods in addition to other topologies and routing algorithms.
引用
收藏
页码：98 / 101
页数：4
相关论文
共 50 条
  • [41] On the Capacity of Bufferless Networks-on-Chip
    Shpiner, Alexander
    Kantor, Erez
    Li, Pu
    Cidon, Israel
    Keslassy, Isaac
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2015, 26 (02) : 492 - 506
  • [42] On the Capacity of Bufferless Networks-on-Chip
    Shpiner, Alexander
    Kantor, Erez
    Li, Pu
    Cidon, Israel
    Keslassy, Isaac
    2012 50TH ANNUAL ALLERTON CONFERENCE ON COMMUNICATION, CONTROL, AND COMPUTING (ALLERTON), 2012, : 770 - 777
  • [43] Asynchronous design of networks-on-chip
    Sparso, Jens
    2007 NORCHIP, 2007, : 225 - 228
  • [44] Statistical Approach to Networks-on-Chip
    Cohen, Itamar
    Rottenstreich, Ori
    Keslassy, Isaac
    IEEE TRANSACTIONS ON COMPUTERS, 2010, 59 (06) : 748 - 761
  • [45] eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
    Beldachi, Arash Farhadi
    Hollis, Simon
    Nunez-Yanez, Jose L.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2014, 8 (03): : 148 - 162
  • [46] Evaluation of energy and buffer aware application mapping for networks-on-chip
    Celik, Cokun
    Bazlamacci, Cuneyt F.
    MICROPROCESSORS AND MICROSYSTEMS, 2014, 38 (04) : 325 - 336
  • [47] Reliability Assessment of Fault Tolerant Routing Algorithms in Networks-on-Chip: An Analytic Approach
    Moriam, Sadia
    Fettweis, Gerhard P.
    PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2017, : 61 - 66
  • [48] A Reliability-Aware Multi-Application Mapping Technique in Networks-on-Chip
    Khalili, Fatemeh
    Zarandi, Hamid R.
    PROCEEDINGS OF THE 2013 21ST EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING, 2013, : 478 - 485
  • [49] LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip
    Chittamuru, Sai Vineel Reddy
    Thakkar, Ishan G.
    Pasricha, Sudeep
    IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, 2018, 4 (04): : 758 - 772
  • [50] SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-Chip
    Chittamuru, Sai Vineel Reddy
    Pasricha, Sudeep
    2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2016, : 86 - 91
12345