On the Capacity of Bufferless Networks-on-Chip

被引:4
|
作者
Shpiner, Alexander [1 ]
Kantor, Erez [2 ]
Li, Pu [3 ]
Cidon, Israel [1 ]
Keslassy, Isaac [1 ]
机构
[1] Technion Israel Inst Technol, Dept Elect Engn, IL-3200003 Haifa, Israel
[2] MIT, CSAIL, Cambridge, MA 02139 USA
[3] ASML, Eindhoven, Netherlands
基金
欧洲研究理事会;
关键词
Networks-on-Chip; bufferless network; scheduling; collective communication; all-to-all personalized exchange; complete-exchange; interprocessor communication; ALL PERSONALIZED COMMUNICATION; COMPLETE EXCHANGE; ALGORITHMS; DESIGN; MODEL; NOC;
D O I
10.1109/TPDS.2014.2310226
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Networks-on-Chip (NoCs) form an emerging paradigm for communications within chips. In particular, bufferless NoCs require significantly less area and power consumption, but also pose novel major scheduling problems to achieve full capacity. In this paper, we provide first insights on the capacity of bufferless NoCs. In particular, we present optimal periodic schedules for several bufferless NoCs with a complete-exchange traffic pattern. These schedules particularly fit distributed-programming models and network congestion-control mechanisms. In addition, for general traffic patterns, we also introduce efficient greedy scheduling algorithms, that often outperform simple greedy online algorithms and cannot have deadlocks. Finally, using network simulations, we quantify the speedup of our suggested algorithms, and show how they improve throughput by up to 35 percent on a torus network.
引用
收藏
页码:492 / 506
页数:15
相关论文
共 50 条
  • [1] On the Capacity of Bufferless Networks-on-Chip
    Shpiner, Alexander
    Kantor, Erez
    Li, Pu
    Cidon, Israel
    Keslassy, Isaac
    [J]. 2012 50TH ANNUAL ALLERTON CONFERENCE ON COMMUNICATION, CONTROL, AND COMPUTING (ALLERTON), 2012, : 770 - 777
  • [2] Wireless on Networks-on-Chip
    Taskin, Baris
    [J]. 2013 ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM LEVEL INTERCONNECT PREDICTION (SLIP), 2013,
  • [3] Routerless Networks-on-Chip
    Alazemi, Fawaz
    Azizimazreah, Arash
    Bose, Bella
    Chen, Lizhong
    [J]. 2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2018, : 492 - 503
  • [4] 3DBUFFBLESS: A Novel Buffered-Bufferless Hybrid Router for 3D Networks-on-Chip
    Tatas, K.
    Savva, S.
    Kyriacou, C.
    [J]. 2017 27TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), 2017,
  • [5] A Case for Bufferless Routing in On-Chip Networks
    Moscibroda, Thomas
    Mutlu, Onur
    [J]. ISCA 2009: 36TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, 2009, : 196 - 207
  • [6] Wormhole Computing in Networks-on-Chip
    Rettkowski, Jens
    Goehringer, Diana
    [J]. 2021 31ST INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2021), 2021, : 273 - 274
  • [7] Communication models in networks-on-chip
    Carara, Everton
    Mello, Aline
    Moraes, Fernando
    [J]. RSP 2007: 18TH IEEE/IFIP INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS, 2007, : 57 - +
  • [8] Approximate Wireless Networks-on-Chip
    Ascia, Giuseppe
    Catania, Vincenzo
    Monteleone, Salvatore
    Palesi, Maurizio
    Patti, Davide
    Jose, John
    [J]. 2018 XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS), 2018,
  • [9] Statistical Approach to Networks-on-Chip
    Cohen, Itamar
    Rottenstreich, Ori
    Keslassy, Isaac
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2010, 59 (06) : 748 - 761
  • [10] Asynchronous design of networks-on-chip
    Sparso, Jens
    [J]. 2007 NORCHIP, 2007, : 225 - 228