5 Gb/s 2:1 fully-integrated full-rate multiplexer with on-chip clock generation circuit in 0.18-μm CMOS

A 5 Gb/s 2:1 full-rate multiplexer (MUX) has been designed and fabricated in SMIC 0.18-mu m CMOS process. A clock generation circuit (CGC) is also integrated to provide the MUX with both 2.5 and 5-GHz clock signals. The CGC is realized by a clock and data recovery (CDR) loop with a divide-by-2 frequency divider embedded in, where the two required clocks are obtained after and before the divider, respectively. In addition, the phase relation between data and clock is assured automatically by CDR feedback loop and the precise layout. The whole chip area is 812 x 675 mu m, including pads. At a single supply voltage of 1.8 V, the total power consumption is 162 mW with an input sensitivity of <25 mV and a single-ended output swing of above 300 mV. And due to the full-rate architecture, the pulse width distortion (PWD) with multiplexed data is removed. The measured results also show that the circuit can work reliably at any input data rate between 2.46 and 2.9 Gb/s without need for external components, reference clock, or manual phase alignment between data and clock.