Package to board interconnect design for minimum return loss

被引:0
|
作者
Sanchez, Adan S. [1 ]
Romo, Gerardo [1 ]
Armenta, Luis F. [1 ]
机构
[1] Intel, Syst Res Ctr Mexico, Tlaquepaque, Jal, Mexico
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Return loss from impedance discontinuities severely limits the bandwidth and power efficiency of chip-to-chip copper interconnects. Among the more frequently found discontinuities are vertical transitions connecting signals in different layers in the system. In this work, we present a general condition to improve return loss in vertical package to board transitions in high speed links. The relationship involves the impedance of on-package and on-board transmission lines as well as the via model. Experimental results that apply the proposed method show a 10-dB improvement in return loss. The proposed method can be applied in the design of copper interconnects with minimum reflection, which is a requirement of high-speed and low-power signaling systems.
引用
收藏
页码:12 / 15
页数:4
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