Efficient bit-parallel systolic architecture for multiplication and squaring over GF(2m)

被引：15

作者：

Kim, Kee-Won ^{[1
]}

Kim, Seung-Hoon ^{[1
]}

机构：

[1] Dankook Univ, Dept Appl Comp Engn, Yongin, South Korea

来源：

IEICE ELECTRONICS EXPRESS | 2018年 / 15卷 / 02期

关键词：

finite field; modular multiplication; squaring; systolic array; cryptography; MULTIPLIERS;

D O I：

10.1587/elex.14.20171195

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this letter, we propose a parallel-in parallel-out systolic array for concurrently computing multiplication and squaring over GF(2(m)). For m >= 400, the proposed bit-parallel systolic array can save about 50% time complexity as compared to the corresponding existing structure. The proposed array can be used as a core circuit for various applications. Also our architecture is well suited to VLSI implementation as well.

引用

页数：6

共 50 条

[1] Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2m)
Hariri, Arash
Reyhani-Masoleh, Arash
[J]. IEEE TRANSACTIONS ON COMPUTERS, 2009, 58 (10) : 1332 - 1345
[2] Fast and Pipelined Bit-Parallel Montgomery Multiplication and Squaring over GF(2m)
Rashidi, Bahram
Sayedi, Sayed Masoud
Farashahi, Reza Rezaeian
[J]. 2015 12TH INTERNATIONAL IRANIAN SOCIETY OF CRYPTOLOGY CONFERENCE ON INFORMATION SECURITY AND CRYPTOLOGY (ISCISC), 2015, : 17 - 22
[3] Efficient Bit-Parallel Systolic Multiplier over GF (2m)
Mozhi, S. Arul
Ramya, P.
[J]. 2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 4899 - 4902
[4] Efficient Bit-Parallel Systolic Multiplier over GF (2m)
Mozhi, S. Arul
Ramya, P.
[J]. 2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 4800 - 4803
[5] Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2m)
Rashidi, Bahram
Sayedi, Sayed Masoud
Farashahi, Reza Rezaeian
[J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2016, 10 (01): : 18 - 29
[6] Efficient Parallel and Serial Systolic Structures for Multiplication and Squaring Over GF(2m)
Ibrahim, Atef
[J]. CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, 2019, 42 (02): : 114 - 120
[7] Compact bit-parallel systolic montgomery multiplication over GF(2m) generated by trinomials
Lee, Chiou-Yng
Chen, Chin-Chin
Lu, Erl-Huei
[J]. TENCON 2006 - 2006 IEEE REGION 10 CONFERENCE, VOLS 1-4, 2006, : 259 - 262
[8] Compact Bit-Parallel Systolic Multiplier Over GF(2m)
Ibrahim, Atef
Gebali, Fayez
Bouteraa, Yassine
Tariq, Usman
Ahanger, Tariq
Alnowaiser, Khaled
[J]. IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING, 2021, 44 (02): : 199 - 205
[9] Bit-Parallel Systolic Architecture for AB and AB2 Multiplications over GF(2m)
Kim, Kee-Won
[J]. IEICE Transactions on Electronics, 2022, E105.C (05) : 203 - 206
[10] Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)
Singh, A. K.
Bera, Asish
Rahaman, H.
Mathew, J.
Pradhan, D. K.
[J]. IEEE CIRCUITS AND SYSTEMS INTERNATIONAL CONFERENCE ON TESTING AND DIAGNOSIS, 2009, : 451 - 454

← 1 2 3 4 5 →