Efficient bit-parallel systolic architecture for multiplication and squaring over GF(2m)

被引：15

作者：

Kim, Kee-Won ^{[1
]}

Kim, Seung-Hoon ^{[1
]}

机构：

[1] Dankook Univ, Dept Appl Comp Engn, Yongin, South Korea

来源：

IEICE ELECTRONICS EXPRESS | 2018年 / 15卷 / 02期

关键词：

finite field; modular multiplication; squaring; systolic array; cryptography; MULTIPLIERS;

D O I：

10.1587/elex.14.20171195

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this letter, we propose a parallel-in parallel-out systolic array for concurrently computing multiplication and squaring over GF(2(m)). For m >= 400, the proposed bit-parallel systolic array can save about 50% time complexity as compared to the corresponding existing structure. The proposed array can be used as a core circuit for various applications. Also our architecture is well suited to VLSI implementation as well.

引用

页数：6

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