Efficient Bit-Parallel Systolic Multiplier over GF (2m)

被引：0
|
作者：
Mozhi, S. Arul [1 ]
Ramya, P. [2 ]
机构：
[1] DMI Coll Engn, Dept ECE, Madras, Tamil Nadu, India
[2] SNS Coll Engn, Madras, Tamil Nadu, India
来源：
2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT) | 2016年
关键词：
Galois field; cryptography; systolic;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A bit parallel systolic multiplier in the finite field GF(2(m)) over the polynomial basis where irreducible polynomial generate the field GF(2(m)) is presented. The complexity of the proposed multiplier is compared in terms of area, latency and speed. The proposed multiplier has high throughput as compared with the traditional systolic multiplier. Moreover, this multiplier is highly regular, modular, and therefore, well-suited for VLSI implementation with fault tolerant design.
引用
收藏
页码：4800 / 4803
页数：4
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