Parallel Pipelined FFT Architecture for Real Valued Signals

被引：0

作者：

Suganya, V ^{[1
]}

Paramasivam, C. ^{[1
]}

机构：

[1] KS Rangasamy Coll Technol, Dept Elect & Commun Engn, Tiruchengode, India

来源：

PROCEEDINGS OF THE 2016 IEEE INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, SIGNAL PROCESSING AND NETWORKING (WISPNET) | 2016年

关键词：

Multipath delay commutator (MDC); Fast Fourier Transform; real valued signals; radix-2(3); radix-2(4); Parallel; pipelining;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Most signal processing applications that uses real valued signals are designed and implemented using Fast Fourier algorithms. The imaginary parts of butterflies are scheduled in place of repeated operation for radix-2(3) and radix-2(4) butterfly structures to deal with the hybrid data path. Along with this scheduling technique folding methodology is used to reduce the redundant samples in the real valued signals. hardware complexity is reduced by using Multiple Delay Commutator (MDC) architecture for parallel samples. As a result of this butterfly structure, hardware complexity, area, power and delay is greatly reduced and the throughput is increased.

引用

页码：2146 / 2149

页数：4

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