Hardware Implementation of the Hirschman Optimal Transform

In this paper, we propose a hardware architecture to compute the Hirschman Optimal Transform (HOT). The HOT promises faster computation than the FFT with reduced area, yet can be used in similar ways. In fact, the HOT can potentially yield faster FIR convolution and superior spectral analysis methods. An N=K-2 point HOT is composed of K, K-point DFTs. For our work, these K-point DFTs are computed using decimation-in-frequency. In this paper, we discuss the implementation details of the HOT. To evaluate the effectiveness of the implementation, we compare the HOT implementation with the FFT implementation for various sizes. We also consider various levels of precision within the implementation. The computational error, space requirements, and maximum throughput are used in the analysis of the implementations. Field Programmable Gate Arrays (FPGAs) are used to implement the algorithms.