Area efficient systolic Multiplier for GF(2m)

被引：0
|
作者：
Kim, HS [1 ]
Kim, YK [1 ]
Yoo, KY [1 ]
机构：
[1] Kyungpook Natl Univ, Taegu 702701, South Korea
来源：
PDPTA'2001: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS | 2001年
关键词：
modular multiplication; systolic array; galois field; partition; pipelining;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a new LSB-first partitioned systolic array for modular multiplication in GF(2(m)) based on standard basis representation. Thereafter, the proposed multiplier is analyzed and compared with a previous multiplier. As compared to the related multiplier presented by Yeh et al the proposed partitioned systolic array requires significantly small number of basic cells. It requires only m/2 number of basic cells and has the same throughput rate as when it is partitioned with the half number of PEs.
引用
收藏
页码：687 / 691
页数：3
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