A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN

被引:0
|
作者
Khandelwal, Shashwat [1 ]
Shreejith, Shanker [1 ]
机构
[1] Trinity Coll Dublin, Dept Elect & Elect Engn, Dublin, Ireland
关键词
Controller Area Network; Intrusion Detection System; Machine Learning; Field Programmable Gate Arrays; INTRUSION DETECTION;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Recent years have seen an exponential rise in complex software-driven functionality in vehicles, leading to a rising number of electronic control units (ECUs), network capabilities, and interfaces. These expanded capabilities also bring-in new planes of vulnerabilities making intrusion detection and management a critical capability; however, this can often result in more ECUs and network elements due to the high computational overheads. In this paper, we present a consolidated ECU architecture incorporating an Intrusion Detection System (IDS) for Automotive Controller Area Network (CAN) along with traditional ECU functionality on an off-the-shelf hybrid FPGA device, with near-zero overhead for the ECU functionality. We propose two quantised multi-layer perceptrons (QMLP's) as isolated IDSs for detecting a range of attack vectors including Denial-of-Service, Fuzzing and Spoofing, which are accelerated using off-the-shelf deep-learning processing unit (DPU) IP block from Xilinx, operating fully transparently to the software on the ECU. The proposed models achieve the state-of-the-art classification accuracy for all the attacks, while we observed a 15x reduction in power consumption when compared against the GPU-based implementation of the same models quantised using Nvidia libraries. We also achieved a 2.3x speed up in permessage processing latency (at 0.24 ms from the arrival of a CAN message) to meet the strict end-to-end latency on critical CAN nodes and a 2.6x reduction in power consumption for inference when compared to the state-of-the-art IDS models on embedded IDS and loosely coupled IDS accelerators (GPUs) discussed in the literature.
引用
收藏
页码:113 / 121
页数:9
相关论文
共 50 条
  • [11] A FPGA-based accelerated architecture for the Continuous GRASP
    Bruno Nogueira
    Erick Barboza
    Computing, 2021, 103 : 1333 - 1352
  • [12] IANUS: Scientific Computing on an FPGA-Based Architecture
    Belletti, Francesco
    Cotallo, Maria
    Cruz, Andres
    Antonio Fernandez, Luis
    Gordillo, Antonio
    Maiorano, Andrea
    Mantovani, Filippo
    Marinari, Enzo
    Martin-Mayor, Victor
    Munoz-Sudupe, Antonio
    Navarro, Denis
    Perez-Gaviro, Sergio
    Rossi, Mauro
    Jesus Ruiz-Lorenzo, Juan
    Fabio Schifano, Sebastiano
    Sciretti, Daniele
    Tarancon, Alfonso
    Tripiccione, Raffaele
    Luis Velasco, Jose
    PARALLEL COMPUTING: ARCHITECTURES, ALGORITHMS AND APPLICATIONS, 2008, 15 : 553 - +
  • [13] An FPGA-based architecture for ECC point multiplication
    Nassar, Doaa
    EI-Kharashi, M. Watheq
    Shousha, Abd El Halim Mahrnoud
    IDT 2007: SECOND INTERNATIONAL DESIGN AND TEST WORKSHOP, PROCEEDINGS, 2007, : 237 - +
  • [14] An Efficient FPGA-based Architecture for Contractive Autoencoders
    Kerner, Madis
    Tammemae, Kalle
    Raik, Jaan
    Hollstein, Thomas
    28TH IEEE INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), 2020, : 230 - 230
  • [15] An FPGA-based integrated environment for computer architecture
    Bulic, Patricio
    Gustin, Veselko
    Sonc, Damjan
    Strancar, Andrej
    COMPUTER APPLICATIONS IN ENGINEERING EDUCATION, 2013, 21 (01) : 26 - 35
  • [16] A FPGA-based accelerated architecture for the Continuous GRASP
    Nogueira, Bruno
    Barboza, Erick
    COMPUTING, 2021, 103 (07) : 1333 - 1352
  • [17] SHARF: AN FPGA-BASED CUSTOMIZABLE PROCESSOR ARCHITECTURE
    Bassoy, Cem Savas
    Manteuffel, Henning
    Mayer-Lindenberg, Friedrich
    FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, : 516 - 520
  • [18] An FPGA-based network intrusion detection architecture
    Das, Abhishek
    Nguven, David
    Zambreno, Joseph
    Memik, Gokhan
    Choudhary, Alok
    IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, 2008, 3 (01) : 118 - 132
  • [19] FPGA-based architecture for motion sequence extraction
    Diaz, J.
    Ros, E.
    Mota, S.
    Rodriguez-Gomez, R.
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2007, 94 (05) : 435 - 450
  • [20] FPGA-based Architecture for Hyperspectral Endmember Extraction
    Rosario, Joao
    Nascimento, Jose M. P.
    Vestias, Mario
    HIGH-PERFORMANCE COMPUTING IN REMOTE SENSING IV, 2014, 9247