FPGA-based architecture for motion sequence extraction

The estimation of motion from image sequences has been widely studied by the scientific community but it is rarely used in real-time applications mainly due to the high computational requirements. A large number of interesting applications (such as robotics, vigilance, sequence compression, etc.) require embedded processing systems which are not yet available. The presented approach implements a novel superpipelined and fully parallelized architecture for optical flow processing with more than 70 pipelined stages that achieve a data throughput of one pixel per clock cycle. The whole system has been implemented into reconfigurable technology to facilitate its adaptation to different application specifications. It achieves high performance computation (148 frames per second at VGA resolution). In this contribution we justify the optical flow model chosen for the implementation, we analyse the presented architecture, and measure the system resource requirements. In particular, we present a massive parallelism design methodology that makes these high performance systems possible. Finally, we evaluate the system comparing its performance with other previous approaches. To the best of our knowledge, the obtained performance is more than one magnitude higher than any previous real-time approach described in the literature.