A fault simulation based test pattern generator for synchronous sequential circuits

被引：11

作者：

Guo, RF ^{[1
]}

Pomeranz, I ^{[1
]}

Reddy, SM ^{[1
]}

机构：

[1] Univ Iowa, Dept Elect & Comp Engn, Iowa City, IA 52242 USA

来源：

17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/VTEST.1999.766674

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at lour computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures.

引用

页码：260 / 267

页数：2

共 50 条

[1] On improving a fault simulation based test generator for synchronous sequential circuits
Guo, RF
Reddy, SM
Pomeranz, I
[J]. 10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 82 - 87
[2] Diagnostic fault simulation for synchronous sequential circuits
Chen, SC
Jou, JM
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (03) : 299 - 308
[3] Hybrid fault simulation for synchronous sequential circuits
Becker, B
Keim, M
Krieger, R
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1999, 15 (03): : 219 - 238
[4] ON FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS
POMERANZ, I
REDDY, SH
[J]. IEEE TRANSACTIONS ON COMPUTERS, 1995, 44 (02) : 335 - 340
[5] Hybrid Fault Simulation for Synchronous Sequential Circuits
Bernd Becker
Martin Keim
Rolf Krieger
[J]. Journal of Electronic Testing, 1999, 15 : 219 - 238
[6] PROPTEST: A property-based test generator for synchronous sequential circuits
Guo, RF
Reddy, SM
Pomeranz, I
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2003, 22 (08) : 1080 - 1091
[7] TEST PATTERN GENERATION FOR SEQUENTIAL MOS CIRCUITS BY SYMBOLIC FAULT SIMULATION
CHO, K
BRYANT, RE
[J]. 26TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, 1989, : 418 - 423
[8] BART: A bridging fault test generator for sequential circuits
Cusey, JP
Patel, JH
[J]. ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, : 838 - 847
[9] Serial diagnostic fault simulation for synchronous sequential circuits
Chen, SC
Jou, JM
[J]. INTEGRATION-THE VLSI JOURNAL, 1997, 23 (02) : 157 - 170
[10] Parallel sequence fault simulation for synchronous sequential circuits
Kung, CP
Lin, CS
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1996, 9 (03): : 267 - 277

← 1 2 3 4 5 →