A fault simulation based test pattern generator for synchronous sequential circuits

被引：11
|
作者：
Guo, RF [1 ]
Pomeranz, I [1 ]
Reddy, SM [1 ]
机构：
[1] Univ Iowa, Dept Elect & Comp Engn, Iowa City, IA 52242 USA
来源：
17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1999年
关键词：
D O I：
10.1109/VTEST.1999.766674
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at lour computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures.
引用
收藏
页码：260 / 267
页数：2
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