Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs:: optimization of the device architecture

被引:128
|
作者
Ernst, T
Tinella, C
Raynaud, C
Cristoloveanu, S
机构
[1] ENSERG, UMR, LPCS, F-38016 Crolles, France
[2] ST Microelectron, F-38920 Crolles, France
[3] CEA, G, DMEL, SPLIT,LETI,CEA, F-38054 Grenoble, France
关键词
SOI; MOSFET; DIBL; full depletion; short-channel effects; fringing field;
D O I
10.1016/S0038-1101(01)00111-3
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Lateral field penetration in the buried oxide (BOX) and underlying substrate of fully depleted SOI MOSFETs is responsible for a dramatic increase of short-channel effects. An original compact model of the latter phenomena is proposed and used to explore optimized architectures of sub-100 nm transistors. Various architectures including the ground-plane MOSFET, are compared using a quasi-2D analysis in order to evaluate the contribution of the BOX to short-channel effects. (C) 2002 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:373 / 378
页数:6
相关论文
共 50 条
  • [1] Experimental analysis of velocity overshoot degradation in sub-0.1 mu m fully-depleted SOI-MOSFETs
    Ohba, R
    Mizuno, T
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1997, 36 (3B): : 1543 - 1547
  • [2] Short channel effects in sub-0.1 mu m SOI-MOSFETs
    Rauly, E
    Balestra, F
    PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES, 1997, 97 (23): : 227 - 232
  • [3] Vertical, fully-depleted, surrounding gate MOSFETs on sub-0.1 mu m thick silicon pillars
    Auth, CP
    Plummer, JD
    1996 54TH ANNUAL DEVICE RESEARCH CONFERENCE DIGEST, 1996, : 108 - 109
  • [4] Short channel effects in sub-0.1μm thin film SOI-MOSFETs
    Rauly, E
    Balestra, F
    ELECTRONICS LETTERS, 1998, 34 (07) : 700 - 701
  • [5] SOI devices for sub-0.1 μm gate lengths
    Colinge, JP
    Park, JT
    Colinge, CA
    2002 23RD INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2002, : 109 - 113
  • [6] Scaling behavior of sub-micron MOSFETs on fully depleted SOI
    Kistler, N
    Woo, J
    SOLID-STATE ELECTRONICS, 1996, 39 (04) : 445 - 454
  • [7] Design criteria for a fully depleted 0.1μm SOI technology
    Burns, JA
    Frankel, RS
    Soares, AM
    Wyatt, PW
    1997 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 78 - 79
  • [8] Simulated device design optimization to reduce the floating body effect for sub-quarter micron fully depleted SOI-MOSFETs
    Koh, R
    Mogami, T
    Kato, H
    IEICE TRANSACTIONS ON ELECTRONICS, 1997, E80C (07) : 893 - 898
  • [9] Simulated device design optimization to reduce the floating body effect for sub-quarter micron fully depleted SOI-MOSFETs
    NEC Corp, Sagamihara-shi, Japan
    IEICE Trans Electron, 7 (893-898):
  • [10] Selective laser annealing (SELA) used in the fabrication of sub-0.1 μM MOSFETs
    Tsukamoto, H
    Suzuki, T
    SOLID-STATE ELECTRONICS, 1998, 42 (04) : 547 - 556