共 50 条
- [31] Structure and process parameter optimization for sub-10nm gate length fully depleted N-type SOI MOSFETs by TCAD modeling and simulation TRANSISTOR SCALING- METHODS, MATERIALS AND MODELING, 2006, 913 : 39 - +
- [32] Advanced Co salicide technology for sub-0.20 μm fully-depleted SOI devices JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2001, 40 (4B): : 2881 - 2886
- [33] Deep sub-0.1-μm MOSFETs with very thin SOI layer for ultralow-power applications ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS, 1998, 81 (11): : 18 - 25
- [34] Pattern density effect of trench isolation-induced mechanical stress on device reliability in sub-0.1 μm technology 2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS, 2004, : 489 - 492
- [37] Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si device parameters IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 177 - 180
- [38] Analysis of the threshold voltage adjustment and floating body effect suppression for 0.1 mu m fully depleted SOI-MOSFET JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1997, 36 (3B): : 1563 - 1568
- [39] Experimental study of impact ionization phenomena in sub-0.1 mu m Si metal-oxide-semiconductor field effect transistors (MOSFETs) JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1996, 35 (2B): : 882 - 886
- [40] HOT-CARRIER EFFECTS IN SUB-0.1 MU-M GATE LENGTH MOSFETS BETWEEN ROOM AND LIQUID-HELIUM TEMPERATURES JOURNAL DE PHYSIQUE IV, 1994, 4 (C6): : 75 - 80