Optimization for SEU/SET immunity on 0.15 μm fully depleted CMOS/SOI digital logic devices

被引：22
|
作者：
Makihara, A. [1 ]
Yamaguchi, T.
Asai, H.
Tsuchiya, Y.
Amano, Y.
Midorikawa, M.
Shindou, H.
Onoda, S.
Hirao, T.
Nakajima, Y.
Takahashi, T.
Ohnishi, K.
Kuboyama, S.
机构：
[1] High Reliabil Components Corp, Tsukuba, Ibaraki 3050033, Japan
[2] Japan Aerosp Explorat Agcy, Tsukuba, Ibaragi 3058505, Japan
[3] Japan Atom Energy Agcy, Takasaki Radiat Chem Res Estab, Takasaki, Gumma 3701292, Japan
[4] Nihon Univ, Funabashi, Chiba 2748501, Japan
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2006年 / 53卷 / 06期
关键词：
commercial process; fully depleted CMOS/SOI; hardness-by-design; SET; SEU;
D O I：
10.1109/TNS.2006.885166
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We designed logic cells hardened for SEUs/SETs using hardness-by-design (HBD) methodology with OKFS 0.15 Am Fully Depleted CMOS/SOI commercial process and these cells were evaluated with sample devices. Our previous work demonstrated that SET-free inverters could be successfully applied as SEU-immune latches. In this work, the logic cells were optimized for SEU/SET immunity up to an LET of 64 MeV/(mg/cm(2)), demonstrating that the process was suitable for space applications with a little penalty.
引用
收藏
页码：3422 / 3427
页数：6
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