Improved gate-edge profile of metal/high-k gate stack using an NH3 ashing process in gate-first CMOSFETs

被引:2
|
作者
Song, SC [1 ]
Zhang, Z [1 ]
Huffman, C [1 ]
Bae, SH [1 ]
Sim, JH [1 ]
Lee, BH [1 ]
机构
[1] SEMATECH, Austin, TX 78741 USA
关键词
13;
D O I
10.1149/1.2131243
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
This study analyzed an alternative ashing technology for removing photoresist in the production of gate-first complementary metal oxide semiconductor field effect transistors (CMOSFETs) with a high-k metal gate stack. NH3 ashing is proposed as an alternative to O-2 ashing to improve the gate-edge profile. It was found that NH3 ashing suppresses bottom oxide growth below the thin HfO2 layer, reducing Si recesses in the source/drain active area, and eliminating bottom oxide encroachment into the gate edge. The NH3 ashing process also makes the HfO2 film more resistant to the wet chemistry, which reduces the high-k undercut beneath the metal gate during the high-k removal process. (c) 2005 The Electrochemical Society. [DOI: 10.1149/1.2131243] All rights reserved.
引用
收藏
页码:G4 / G6
页数:3
相关论文
共 50 条
  • [21] A cost effective 32nm high-k/metal gate CMOS technology for low power applications with single-metal/gate-first process
    Chen, X.
    Samavedam, S.
    Narayanan, V.
    Stein, K.
    Hobbs, C.
    Baiocco, C.
    Li, W.
    Jaeger, D.
    Zaleski, M.
    Yang, H. S.
    Kim, N.
    Lee, Y.
    Zhang, D.
    Kang, L.
    Chen, J.
    Zhuang, H.
    Sheikh, A.
    Wallner, J.
    Aquilino, M.
    Han, J.
    Jin, Z.
    Li, J.
    Massey, G.
    Kalpat, S.
    Jha, R.
    Moumen, N.
    Mo, R.
    Kirshnan, S.
    Wang, X.
    Chudzik, M.
    Chowdhwy, M.
    Nair, D.
    Reddy, C.
    Teh, Y. W.
    Kothandaraman, C.
    Coolbaugh, D.
    Pandey, S.
    Tekleab, D.
    Thean, A.
    Sherony, M.
    Lage, C.
    Sudijono, J.
    Lindsay, R.
    Ku, J. H.
    Khare, M.
    Steegen, A.
    2008 SYMPOSIUM ON VLSI TECHNOLOGY, 2008, : 67 - +
  • [22] Process and manufacturing challenges for high-K gate stack systems
    Gilmer, MC
    Luo, TY
    Huff, HR
    Jackson, MD
    Kim, S
    Bersuker, G
    Zeitzoff, P
    Vishnubhotla, L
    Brown, GA
    Amos, R
    Brady, D
    Watt, VHC
    Gale, G
    Guan, J
    Nguyen, B
    Williamson, G
    Lysaght, P
    Torres, K
    Geyling, F
    Gondran, CFH
    Fair, JA
    Schulberg, MT
    Tamagawa, T
    ULTRATHIN SIO2 AND HIGH-K MATERIALS FOR ULSI GATE DIELECTRICS, 1999, 567 : 323 - 341
  • [23] A cost effective 32nm high-k/metal gate CMOS technology for low power applications with single-metal/gate-first process
    Chen, X.
    Samavedam, S.
    Narayanan, V.
    Stein, K.
    Hobbs, C.
    Baiocco, C.
    Li, W.
    Jaeger, D.
    Zaleski, M.
    Yang, H. S.
    Kim, N.
    Lee, Y.
    Zhang, D.
    Kang, L.
    Chen, J.
    Zhuang, H.
    Sheikh, A.
    Wallner, J.
    Aquilino, M.
    Han, J.
    Jin, Z.
    Li, J.
    Massey, G.
    Kalpat, S.
    Jha, R.
    Moumen, N.
    Mo, R.
    Kirshnan, S.
    Wang, X.
    Chudzik, M.
    Chowdhury, M.
    Nair, D.
    Reddy, C.
    Teh, Y. W.
    Kothandaraman, C.
    Coolbaugh, D.
    Pandey, S.
    Tekleab, D.
    Thean, A.
    Sherony, M.
    Lage, C.
    Sudijono, J.
    Lindsay, R.
    Ku, J. H.
    Khare, M.
    Steegen, A.
    2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, : 88A - 89A
  • [24] Investigation of Gate Etch Damage at Metal/High-k Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current
    Cho, Heung-Jae
    Son, Younghwan
    Oh, Byoungchan
    Jang, Seunghyun
    Lee, Jong-Ho
    Park, Byung-Gook
    Shin, Hyungcheol
    IEEE ELECTRON DEVICE LETTERS, 2011, 32 (04) : 569 - 571
  • [25] High-k metal gate MOSFETs:: Impact of extrinsic process condition on the gate-stack quality -: A mobility study
    Trojman, Lionel
    Ragnarsson, Lars-Ake
    O'Sullivan, Barry J.
    Rosmeulen, Maarten
    Kaushik, Vidya S.
    Groeseneken, Guido V.
    Maes, Herman E.
    De Gendt, Stefan
    Heyns, Marc
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (03) : 497 - 503
  • [26] Electrical Properties and Interfacial Structures of High-k/Metal Gate MOSCAP using Ti/TiN Scavenging Stack between High-k Dielectric and Metal Gate
    Ma, Xueli
    Wang, Xiaolei
    Han, Kai
    Wang, Wenwu
    Yang, Hong
    Zhao, Chao
    Chen, Dapeng
    Ye, Tianchun
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2013 (CSTIC 2013), 2013, 52 (01): : 117 - 121
  • [27] Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond
    Choi, K.
    Jagannathan, H.
    Choi, C.
    Edge, L.
    Ando, T.
    Frank, M.
    Jamison, P.
    Wang, M.
    Cartier, E.
    Zafar, S.
    Bruley, J.
    Kerber, A.
    Linder, B.
    Callegari, A.
    Yang, Q.
    Brown, S.
    Stathis, J.
    Iacoponi, J.
    Paruchuri, V.
    Narayanan, V.
    2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : A138 - A139
  • [28] Sub-nanometer high-K gate stack scaling using the HF-last/NH3 anneal interface
    Peterson, JJ
    Barnett, J
    Young, CD
    Hou, TH
    Gutt, J
    Gopalan, S
    Lee, CH
    Li, HJ
    Moumen, N
    Chaudhary, N
    Lee, BH
    Bersuker, G
    Zeitzoff, PM
    Brown, GA
    Lysaght, P
    Gardner, M
    Murto, RW
    Huff, HR
    CLEANING TECHNOLOGY IN SEMICONDUCTOR DEVICE MANUFACTURING VIII, 2004, 2003 (26): : 93 - 99
  • [29] A Cost-Conscious 32nm CMOS Platform Technology with Advanced Single Exposure Lithography and Gate-First Metal Gate/High-K Process
    Hasegawa, S.
    Kitamura, Y.
    Takahata, K.
    Okamoto, H.
    Hirai, T.
    Miyashita, K.
    Ishida, T.
    Aizawa, H.
    Aota, S.
    Azuma, A.
    Fukushima, T.
    Harakawa, H.
    Hasegawa, E.
    Inohara, M.
    Inumiya, S.
    Ishizuka, T.
    Iwamoto, T.
    Kariya, N.
    Kojima, K.
    Komukai, T.
    Matsunaga, N.
    Mimotogi, S.
    Muramatsu, S.
    Nagatomo, K.
    Nagahara, S.
    Nakahara, Y.
    Nakajima, K.
    Nakatsuka, K.
    Nishigoori, M.
    Nomachi, A.
    Ogawa, R.
    Okada, N.
    Okamoto, S.
    Okano, K.
    Oki, T.
    Onoda, H.
    Sasaki, T.
    Satake, M.
    Suzuki, T.
    Suzuki, Y.
    Tagami, M.
    Takeda, K.
    Tanaka, M.
    Taniguchi, K.
    Tominaga, M.
    Tsutsui, G.
    Utsumi, K.
    Watanabe, S.
    Watanabe, T.
    Yoshimizu, Y.
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, 2008, : 938 - +
  • [30] Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond
    Choi, K.
    Jagannathan, H.
    Choi, C.
    Edge, L.
    Ando, T.
    Frank, M.
    Jamison, P.
    Wang, M.
    Cartier, E.
    Zafar, S.
    Bruley, J.
    Kerber, A.
    Linder, B.
    Callegari, A.
    Yang, Q.
    Brown, S.
    Stathis, J.
    Iacoponi, J.
    Paruchuri, V.
    Narayanan, V.
    2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2009, : 138 - +