Improved gate-edge profile of metal/high-k gate stack using an NH3 ashing process in gate-first CMOSFETs

被引:2
|
作者
Song, SC [1 ]
Zhang, Z [1 ]
Huffman, C [1 ]
Bae, SH [1 ]
Sim, JH [1 ]
Lee, BH [1 ]
机构
[1] SEMATECH, Austin, TX 78741 USA
关键词
13;
D O I
10.1149/1.2131243
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
This study analyzed an alternative ashing technology for removing photoresist in the production of gate-first complementary metal oxide semiconductor field effect transistors (CMOSFETs) with a high-k metal gate stack. NH3 ashing is proposed as an alternative to O-2 ashing to improve the gate-edge profile. It was found that NH3 ashing suppresses bottom oxide growth below the thin HfO2 layer, reducing Si recesses in the source/drain active area, and eliminating bottom oxide encroachment into the gate edge. The NH3 ashing process also makes the HfO2 film more resistant to the wet chemistry, which reduces the high-k undercut beneath the metal gate during the high-k removal process. (c) 2005 The Electrochemical Society. [DOI: 10.1149/1.2131243] All rights reserved.
引用
收藏
页码:G4 / G6
页数:3
相关论文
共 50 条
  • [41] Challenges in spacer process development for leading-edge high-k metal gate technology
    Koehler, Fabian
    Triyoso, Dina H.
    Hussain, Itasham
    Antonioli, Bianca
    Hempel, Klaus
    PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 11, NO 1, 2014, 11 (01): : 73 - 76
  • [42] An improved pregate cleaning process for high-k gate dielectric fabrication
    Kang, JF
    Yu, HY
    Ren, C
    Liu, XY
    Han, RQ
    Yu, B
    Kwong, DL
    ELECTROCHEMICAL AND SOLID STATE LETTERS, 2005, 8 (11) : G314 - G316
  • [43] Characterization of high-K/metal gate using picosecond ultrasonics
    Hsieh, D. B.
    Tsai, T. C.
    Huang, S. F.
    Yang, Y. R.
    Yang, C. L.
    Wu, J. Y.
    Dai, J.
    Chen, J.
    Tan, J.
    Mukundhan, P.
    MICROELECTRONIC ENGINEERING, 2011, 88 (05) : 583 - 588
  • [44] Applicable solvent photoresist strip process for high-k/metal gate
    Wada, M.
    Takahashi, H.
    Snow, J.
    Vos, R.
    Mertens, P. W.
    Shirakawa, H.
    ULTRA CLEAN PROCESSING OF SEMICONDUCTOR SURFACES X, 2012, 187 : 105 - +
  • [45] Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes
    Choi, Changhwan
    Ando, Takashi
    Cartier, Eduard
    Frank, Martin M.
    Iijima, Ryosuke
    Narayanan, Vijay
    MICROELECTRONIC ENGINEERING, 2009, 86 (7-9) : 1737 - 1739
  • [46] Fluorine interface treatments within the gate stack for defect passivation in 28nm high-k metal gate technology
    Drescher, Maximilian
    Naumann, Andreas
    Sundqvist, Jonas
    Erben, Elke
    Grass, Carsten
    Trentzsch, Martin
    Lazarevic, Florian
    Leitsmann, Roman
    Plaenitz, Philipp
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2015, 33 (02):
  • [47] Breakdown in the metal/high-k gate stack: Identifying the "weak link" in the multilayer dielectric
    Bersuker, G.
    Heh, D.
    Young, C.
    Park, H.
    Khanal, P.
    Larcher, L.
    Padovani, A.
    Lenahan, P.
    Ryan, J.
    Lee, B. H.
    Tseng, H.
    Jarnmy, R.
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, 2008, : 791 - +
  • [48] Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process
    Zhang ShuXiang
    Yang Hong
    Tang Bo
    Tang Zhaoyun
    Xu Yefeng
    Xu Jing
    Yan Jiang
    JOURNAL OF SEMICONDUCTORS, 2014, 35 (10)
  • [49] Combining a multi deposition multi annealing technique with a scavenging(Ti) to improve the high-k/metal gate stack performance for a gate-last process
    张淑祥
    杨红
    唐波
    唐兆云
    徐烨峰
    许静
    闫江
    Journal of Semiconductors, 2014, 35 (10) : 186 - 190
  • [50] Damascene Metal Gate Technology for Damage-free Gate-Last High-k Process Integration
    Endres, Ralf
    Krauss, Tillmann
    Wessely, Frank
    Schwalke, Udo
    2009 3RD INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS (SCS 2009), 2009, : 43 - 45