A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SETs

被引：3

作者：

Fazeli, M. ^{[1
]}

Miremadi, S. G. ^{[1
]}

机构：

[1] Sharif Univ Technol, Dept Comp Engn, Tehran, Iran

来源：

23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/DFT.2008.33

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (Single Event Transient and Upset Robust latch) is presented and evaluated The SETUR is based on the use of a redundant feedback line and a CMOS delay element to tolerate the effect of the SETs occurring in the input line of the latch as well as SEUs occurring inside the latch. The experimental results shou, that the probability, of an SET resulting in a soft error can be reduced up to 90% by choosing a proper delay value. The soft error rate of the SETUR due to SEW occurring inside the latch is reduced by 95% while having lower area, power and performance overhead than the previously proposed latches.

引用

页码：193 / 201

页数：9

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