Hardening FPGA-based systems against SEUs: A new design methodology

被引：0

作者：

Sterpone, L. ^{[1
]}

Violante, M. ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Automat & Informat, Turin, Italy

来源：

JOURNAL OF COMPUTERS | 2006年 / 1卷 / 01期

关键词：

FPGA; SEU; fault tolerance;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarks circuits and on a realistic circuit to show the capabilities of the proposed design flow.

引用

页码：22 / 30

页数：9

共 50 条

[1] On the Effects of Cumulative SEUs in FPGA-based Systems
Nunes, Jose Luis
Cunha, Joao Carlos
Zenha-Rela, Mario
[J]. 2016 12TH EUROPEAN DEPENDABLE COMPUTING CONFERENCE (EDCC 2016), 2016, : 89 - 96
[2] Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs
Zarandi, Hamid R.
Miremadi, Seyed Ghassem
[J]. MICROELECTRONICS RELIABILITY, 2007, 47 (2-3) : 461 - 470
[3] A methodology to design FPGA-based PID controllers
Lima, Joao
Menotti, Ricardo
Cardoso, Joao M. P.
Marques, Eduardo
[J]. 2006 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS, VOLS 1-6, PROCEEDINGS, 2006, : 2577 - +
[4] DeMAS: An Efficient Design Methodology for Building Approximate Adders for FPGA-Based Systems
Prabakaran, Bharath Srinivas
Rehman, Semeen
Hanif, Muhammad Abdullah
Ullah, Salim
Mazaheri, Ghazal
Kumar, Akash
Shafique, Muhammad
[J]. PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018, : 917 - 920
[5] SysML Methodology for FPGA-based Controller Design for Quadcopters
Dominguez-Bonilla, Camilo
Gutierrez, Alonso
Jimenez, Fernando
Chamorro, Harold R.
[J]. 7TH IEEE ANNUAL INFORMATION TECHNOLOGY, ELECTRONICS & MOBILE COMMUNICATION CONFERENCE IEEE IEMCON-2016, 2016,
[6] Methodology for CNN Implementation in FPGA-Based Embedded Systems
Zacchigna, Federico G.
[J]. IEEE EMBEDDED SYSTEMS LETTERS, 2023, 15 (02) : 85 - 88
[7] A design flow for protecting FPGA-based systems against single event upsets
Sterpone, L
Violante, M
[J]. DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, 2005, : 436 - 444
[8] Novel Digital NGD Methodology for FPGA-Based Embedded Systems
Randriatsiferana, Rivo
Lorandel, Jordane
Salvador, Ruben
Moy, Christophe
[J]. IEEE ACCESS, 2024, 12 : 71520 - 71534
[9] A new RTL debugging methodology in FPGA-based verification platform
Yang, SJ
Shim, H
Yang, WS
Kyung, CM
[J]. PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 180 - 183
[10] A methodology for FPGA-based control implementation
Fang, ZW
Carletta, JE
Veillette, RJ
[J]. IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY, 2005, 13 (06) : 977 - 987

← 1 2 3 4 5 →