A design flow for protecting FPGA-based systems against single event upsets

被引：7

作者：

Sterpone, L ^{[1
]}

Violante, M ^{[1
]}

机构：

[1] Politecn Torino, Turin, Italy

来源：

DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS | 2005年

关键词：

D O I：

10.1109/DFTVS.2005.5

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarks circuits and on a realistic circuit to show the capabilities of the proposed design flow.

引用

页码：436 / 444

页数：9

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