Hardening FPGA-based systems against SEUs: A new design methodology

被引：0

作者：

Sterpone, L. ^{[1
]}

Violante, M. ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Automat & Informat, Turin, Italy

来源：

JOURNAL OF COMPUTERS | 2006年 / 1卷 / 01期

关键词：

FPGA; SEU; fault tolerance;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarks circuits and on a realistic circuit to show the capabilities of the proposed design flow.

引用

页码：22 / 30

页数：9

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