The design and implementation of a power efficient embedded SRAM

With the rapid development of silicon technology, gate and wire delays become unpredictable, which makes synchronous timing become difficult in future VLSI design. Self-timed circuits offer reliable operations under any arbitrary gate and wire delays. In the paper, a transistor-level register bank is proposed for deep sub-micron silicon technology. The register file shows a good characteristic of robustness under very low voltage. The register bank is also very cost- and power-efficient, making it suitable for embedded processing systems with tight area and power budget, such as sensor network microprocessors. Portable and battery-powered applications call for long battery life, which makes the requirements of these devices shift from high performance to power efficiency. Many design methods and architectures have been proposed to increase the power efficiency of digital circuits. However, as people's requests for low power will never be satisfied, power efficient design methods and architectures will never be enough. In this paper, a coprocessor, using a dataflow scheme and an asynchronous logic control, is embedded in a conventional microprocessor to minimize its power consumption. The circuit implementation of the asynchronous dataflow coprocessor and the communicate scheme with the outside environment are presented in the paper.