Workload Dependent NBTI and PBTI Analysis for a sub-45nm Commercial Microprocessor

被引：0

作者：

Mintarno, Evelyn ^{[1
]}

Chandra, Vikas ^{[2
]}

Pietromonaco, David ^{[2
]}

Aitken, Robert ^{[2
]}

Dutton, Robert W. ^{[1
]}

机构：

[1] Stanford Univ, Stanford, CA 94305 USA

[2] ARM R&D, Sunnyvale, CA USA

来源：

2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper analyzes aging effects on various design hierarchies of a sub-45nm commercial processor running realistic applications. Dependencies of aging effects on switching-activity and power-state of workloads are quantified. This paper presents an "instance-based" simulation flow, which creates a standard-cell library for each use of the cell in the design, by aging each transistor individually. Implementation results show that processor timing degradation can vary from 2% to 11%, depending on workload. Lifetime computational power efficiency improvements of optimized self-tuning is demonstrated, relative to a one-time worst-case guardbanding approach.

引用

页数：6

共 46 条

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