Novellus launches SOLA xT UVTP system for sub-45nm HVM

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SOLID STATE TECHNOLOGY | 2010年 / 53卷 / 03期
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TM [电工技术]; TN [电子技术、通信技术];
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  • [1] Partners share the costs of sub-45nm research
    不详
    [J]. IEE REVIEW, 2004, 50 (11): : 12 - 12
  • [2] Infusion Doping for Sub-45nm CMOS Technology Nodes
    Kalra, Pankaj
    Majhi, Prashant
    Tseng, Hsing-Huang
    Jammy, Raj
    Liu, Tsu-Jae King
    [J]. ION IMPLANTATION TECHNOLOGY 2008, 2008, 1066 : 407 - +
  • [3] Electrical characteristic fluctuations in sub-45nm CMOS devices
    Yang, Fu-Liang
    Hwang, Jiunn-Ren
    Li, Yiming
    [J]. PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, : 691 - 694
  • [4] Effective Drive Current in CMOS Inverters for Sub-45nm Technologies
    Hu, Jenny
    Park, Jae-Eun
    Freeman, Greg
    Wachnik, Richard
    Wong, H. -S. Philip
    [J]. NSTI NANOTECH 2008, VOL 3, TECHNICAL PROCEEDINGS: MICROSYSTEMS, PHOTONICS, SENSORS, FLUIDICS, MODELING, AND SIMULATION, 2008, : 829 - +
  • [5] CHARACTERIZATION, MODELLING AND SIMULATION OF SUB-45NM SOI DEVICES
    Rodriguez, Noel
    Gamiz, Francisco
    Cristoloveanu, Sorin
    [J]. CAS: 2009 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2009, : 57 - +
  • [6] Lithography options and challenges for sub-45nm node interconnect layers
    Maenhoudt, M.
    [J]. PROCEEDINGS OF THE IEEE 2008 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2008, : 70 - 72
  • [7] Workload Dependent NBTI and PBTI Analysis for a sub-45nm Commercial Microprocessor
    Mintarno, Evelyn
    Chandra, Vikas
    Pietromonaco, David
    Aitken, Robert
    Dutton, Robert W.
    [J]. 2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2013,
  • [8] A low-temperature LPCVD silicon - nitride process for sub-45nm
    Chiu, E.
    Kolessov, A.
    Mohamed, K.
    Su, J.
    [J]. SOLID STATE TECHNOLOGY, 2007, 50 (12) : 42 - 43
  • [9] New generation of predictive technology model for sub-45nm design exploration
    Zhao, Wei
    Cao, Yu
    [J]. ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 585 - +
  • [10] Enhanced Layout Optimization of Sub-45nm Standard, Memory Cells and Its Effects
    Paek, Seung Weon
    Jang, Dae Hyun
    Park, Joo Hyun
    Ha, Naya
    Kim, Byung-Moo
    Won, Hyo Sig
    Choi, Kyu-Myung
    Lin, Kuang-Kuo
    Klaver, Simon
    Malik, Shobhit
    Oostindie, Michiel
    Driessen, Frank
    [J]. DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION III, 2009, 7275
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