Effective Drive Current in CMOS Inverters for Sub-45nm Technologies

We propose a new model for the effective drive current (I-eff) of CMOS inverters, where the maximum FET current obtained during inverter switching (I-PEAK) is a key parameter. I-eff is commonly defined as the average between I-H and I-L, where I-H = I-ds(V-gs = V-DD, V-ds = 0.5V(DD)) and I-L = I-ds(V-gs = 0.5V(DD), V-ds = V-DD). In the past, this I-eff definition has been accurate in modeling the inverter delay. However, we find that as devices are scaled further into the nanoscale regime, the maximum transient current can deviate severely from I-H, in which case, another metric should be used. The deviation Of I-PEAK from I-H is found to increase as delay decreases or as device overdrive voltage increases. We define I-eff = (I-PEAK+I-M+I-L)/ 3, where I-M = I-ds(V-gs = 0.75V(DD), V-ds = 0.75V(DD)). We evaluate our model against others by comparing the analytical and HSPICE extracted I-eff ratios across devices of varying threshold voltages, V-TH. Our model is shown to better capture changes in V-TH/V-DD, which are important since V-DD and V-TH will be key parameters for optimizing device performances for target applications (low power or high performance) in sub-45nm technologies.